This invention relates to a new and improved castellation via process which can prevent causing xe2x80x9cshort circuitxe2x80x9d and/or xe2x80x9copen circuitxe2x80x9d problems due to burrs and dust particles generated in the traditional manufacturing processes.
Traditionally, Leadless Chip Carrier is manufactured with ceramic materials and processes, at very high cost. In order to reduce cost, plastic chip carrier was developed as a replacement for the ceramic leadless chip carrier, whereas the cost saving is around 3 to 1 reduction. Note that one essential aspect for the new plastic carrier 220 to be a functioning replacement of its ceramic predecessor is the capability to provide high quality structure and surface finish in the half-cylinder shaped (castellation) side contact pins 135, which are made by routing out one-half of a full-cylinder plated through hole. But the prior art in manufacturing such plastic chip carrier is prone to the phenomenon of xe2x80x9cburrxe2x80x9d 310, which causes many problems including open circuit and short circuit immediately after fabrication and during the useful life cycle of the product.
The object of the present invention is to provide a new and improved castellation via process which can prevent causing short circuit and open circuit problems due to burrs and dust particles generated in the traditional manufacturing process. According to the invention, burrs and dust particles are eliminated or minimized in the process of manufacturing leadless semiconductor chip carriers which include copper plating the carrier substrate to form a copper plated chip carrier substrate and wherein the routing of one or more slots in the copper plated chip carrier substrate. The improvement comprises preventing burrs wherein the copper plating is performed prior to making the routing of one or more slots by a thin plating in a thickness range of about 2 microns to about 6 microns. Subsequent to routing of the slots, the copper is thickened by plating to a thickness of the final thickness range, preferably in the range of 15 to 25 microns. In a further aspect of the process, a protective coating layer, such as an ultraviolet (UV) curable ink is applied after the thin copper plating. The UV curable ink layer provides protection for the thin copper layer during routing and is stripped off or removed after routing. The UV coating layer provides backing support and prevents the thin copper from being pulled off and forming burrs during routing.
This results in a leadless semiconductor chip carrier having copper plating on a substrate and one or more machine routings formed through the copper plating and substrate wherein the improvement lies in the copper plating being comprised of a first thin copper layer (having a thickness range of about 2 to 6 microns) and applied prior to the machine routings. At least one thicker copper layer is applied after the machine routing so that the thickness of the copper plating is preferably in the range of from about 15 microns to about 25 microns.